1. Field of Invention
The present invention relates to a method of manufacturing a static random access memory (SRAM). More particularly, the present invention relates to a method of fabricating a buried contact in the SRAM.
2. Description of Related Art
Since static random access memory (SRAM) is one of the fastest operating semiconductor memory devices, it is widely used in computer equipment for the storage and retrieval of data. At present, SRAMs are extensively used in digital products including microcomputers and microprocessor systems.
In general, a SRAM can be divided into two structural regions, namely a memory cell region and a peripheral circuit region. The memory cell is used for storing binary data, whereas, the peripheral circuit region has a number of address decoders, which are used to decode memory cell addresses issued from the memory cell region as well as to control related memory circuits. FIG. 1 is a diagram showing the circuit of a conventional SRAM cell.
As shown in FIG. 1, a typical SRAM memory cell comprises resistors (or reactance elements) R.sub.1, R.sub.2, and MOS transistors T.sub.1, T.sub.2, T.sub.3 and T.sub.4. The resistor R.sub.1 and the MOS transistor T.sub.1 are connected in series, and the drain terminal and the source terminal of the MOS transistor T.sub.1 are connected to a voltage source V.sub.DD and a ground line V.sub.SS, respectively. Similarly, the resistor R.sub.2 and the MOS transistor T.sub.2 are connected in series, and the drain terminal and the source terminal of the MOS transistor T.sub.2 are connected to the voltage source V.sub.DD and the ground line V.sub.SS, respectively.
The gate terminal of the MOS transistor T.sub.2, the drain terminal of the MOS transistor T.sub.1 and the drain terminal of the MOS transistor T.sub.3 are electrically connected at node point A. Similarly, at node point B, the gate terminal of the MOS transistor T.sub.1, the drain terminal of the MOS transistor T.sub.2 and the drain terminal of the MOS transistor T.sub.4 are connected together. The gate terminals of MOS transistors T.sub.3 and T.sub.4 are both connected to a word line WL, whereas the source terminals of the MOS transistors T.sub.3 and T.sub.4 are connected to a bit line BL and a complementary bit line BL, respectively. Functionally, the transistors T.sub.1 and T.sub.2 act as drivers, the transistors T.sub.3 and T.sub.4 act as storage and retrieval controllers for accessing the data stored inside the memory cell, and the resistors R.sub.1 and R.sub.2 serve as loads.
In the past, most SRAM contact window structures are formed above the source/drain region. However, due to the need for highly integrated circuits, conventional contact window structures have become inefficient. Consequently, a buried contact window structure suitable for fabricating local interconnects is invented. The buried contact structure is capable of reducing area occupation by up to 25%, for example, in SRAM. Hence, a buried contact window structure is indispensable in the fabrication of high-density electronic products.
Conventionally, a buried contact window is formed by depositing a polysilicon layer over the buried contact window region of a substrate. Then, the substrate is heated, allowing the dopants in the polysilicon layer to diffuse into the silicon substrate. The doped polysilicon layer remaining above the buried contact window region acts as a contact between the buried contact window region and conductive line. However, should misalignment occur when the polysilicon layer is etched, a portion of the substrate inside the buried contact window region will be exposed. As the polysilicon layer is over-etched, a buried contact window trench will be formed. The presence of this buried contact window trench will interfere with the transistor's current flow path, thereby leading to device malfunction.
To understand the situation better, the process of fabricating a conventional SRAM is described with reference to FIGS. 2A through 2I. FIGS. 2A through 2I are cross-sectional views showing a conventional method of fabricating a static random access memory.
As shown in FIG. 2A, a semiconductor substrate 200 is provided. The substrate 200 has a device isolating structure, for example, shallow trench isolation (STI) 202. A gate oxide layer 204 is formed on the semiconductor substrate 200, and then a conductive layer 206 is formed on the gate oxide layer 204. The conductive layer 206 and the gate oxide layer 204 are patterned to expose the substrate region between the STI region 202 and the conductive layer 206/gate oxide layer 204. The exposed substrate region 207 between the STI region 202 and the conductive layer 206/gate oxide layer 204 is the region for forming a buried contact window.
Next, as shown in FIG. 2B, an ion implantation is carried out, to implant ions into the desired contact window region in the semiconductor substrate 200 (the arrows as shown in FIG. 2B). Subsequently, conventional annealing is applied to form a heavily doped N.sup.+ region 208.
Next, as shown in FIG. 2C, a conductive layer 216 is deposited over the semiconductor substrate 200. A metal silicide layer 212 is formed on the conductive layer 216 to lower the resistance between the heavily doped N.sup.+ region 208 in the buried contact window region and a conductive line.
Next, as shown in FIG. 2D, a gate patterning process is performed. In other words, a photoresist layer (not shown) is formed on the metal silicide layer 212. Then, a multi-layered stack including the metal silicide layer 212, the conductive layer 216 and the conductive layer 206 are etched. Hence, a gate 217 and a conductive line 227 electrically coupled to the heavily doped N.sup.+ region 208 are formed.
However, the heavily doped N.sup.+ region 208, the conductive layer 216 and the conductive layer 206 are all made from the same material. Hence, in the aforementioned gate processing operation, should misalignment occur, a trench 209 is formed in the heavily doped N.sup.+ region of the buried contact window region. The size of the trench 209 depends on the degree of over-etching. If the degree of over-etching is small, a shallow trench 209 is formed. A shallow trench in the heavily doped N.sup.+ region reduces the cross-sectional area of the heavily doped N.sup.+ region 208 in the buried contact window region, thus leading to an increase in resistance. On the other hand, if the degree of over-etching is large, a deep trench 209 is formed. A deep trench in the heavily doped N.sup.+ region cuts off its connection with subsequently formed source/drain region to make an open-circuit.
Next, as shown in FIG. 2E, another ion implantation (arrows 220 in FIG. 2E) is performed to form a source/drain region 237 in the substrate 200. In other words, using the gate 217 and the conductive layer 227 as masks, ions are implanted into the exposed semiconductor substrate 200 in region labeled 237. Then, the substrate 200 is annealed to form a lightly doped N.sup.- region 218.
Next, as shown in FIG. 2F, an insulating layer is deposited over the semiconductor substrate 200, covering the gate 217, the conductive line 227 and the lightly doped N.sup.- region 218. An anisotropic etching is carried out to the insulating layer to form spacers 224 on the sidewalls of the gate 217 and the conductive line 227. The spacers 224 cover a portion of the lightly doped N.sup.- region 218. Consequently, the spacer 224 can be used as a mask for forming the heavily doped region with a lightly doped drain (LDD) structure.
As shown in FIG. 2G, yet another ion implantation (arrows labeled 218 in FIG. 2G) is carried out implanting ions into the source/drain region. In other words, ions having a high concentration are implanted into the lightly doped N.sup.- region 218. The substrate 200 is annealed to form a source/drain region having a lightly doped drain (LDD) structure, in which the LDD structure includes the lightly doped N.sup.- region 218 and the heavily doped N.sup.+ region 228. Since a portion of the substrate 200 is covered by spacer 224, very few ions can have sufficient penetrating power to end up in that region. Therefore, regions having different dopant concentration are produced. Up to this stage, a complete buried contact window of an SRAM cell is fabricated.
As shown in FIG. 2H, a dielectric layer 238, commonly an oxide layer, is formed over the substrate 200 by CVD. A chemical mechanical polishing (CMP) method is performed for planarization of the dielectric layer to make the dielectric layer and a subsequently formed via having the same surface level. Thereafter, a via 242 is formed in the dielectric layer 238 to expose the metal silicide layer 212 for forming the desired via 242 by a photolithography and an etching methods.
As shown in FIG. 2I, a poly load 244 is formed along the via 242 for being electrically coupled to the metal silicide layer 212. The step is preferably to form a polysilicon layer conformal to the dielectric layer 238 and the via 242 by CVD. Then, the polysilicon layer is patterned to form a polysilicon conductive line. An ion implantation is performed for adjusting the resistance of the polysilicon conductive layer to form the poly load 244.
In summary, the conventional method can easily lead to the over-etching of the heavily doped N.sup.+ region 208 in the buried contact window region when the gate 217 and the conductive line 227 are etched. Consequently, trench 209 is formed. Moreover, the size of the trench 209 depends on the degree of over-etching. If the degree of over-etching is small, a shallow trench 209 is formed. A shallow trench in the heavily doped N.sup.+ region will reduce the cross-sectional area of the heavily doped N.sup.+ region 208 in the buried contact window region, thus leading to an increase in resistance. On the other hand, if the degree of over-etching is large, a deep trench 209 is formed. A deep trench in the heavily doped N.sup.+ region cuts off its connection with subsequently formed source/drain region.
In light of the foregoing, there is a need to provide an improved method of forming buried contact window in SRAM cell.